1. Field of the Invention
The present invention relates to wafer processing methods and, more particularly, to efficient and cost effective etch operations for wafers.
2. Description of the Related Art
Modern microchip designs have been trending toward ever more complicated chip structures and toward increased numbers of processing steps for a single chip. In particular, the number of interconnected metal layers stacked on top of each other has grown continuously over the past. With it, the number of plasma processing steps and the amount of thermal and electric stress each wafer incurs during its processing have increased as well. As a result of this enhanced complexity in chip manufacturing plasma induced damage may occur more frequently leading to device destruction and, therefore, to yield losses on a product wafer.
In typical wafer etching operations, the wafer is clamped by an electrostatic chuck (ESC) so that the wafer does not move during wafer etching operation. Under prior art operations, a high voltage is typically applied to the electrodes of the ESC. The electro-static field developed in response of the applied voltage produces an attractive force between the wafer and the ESC. However, as soon as plasma is struck, the wafer potential is generally driven to a negative value with respect to the chamber walls within a few dozen RF cycles. Furthermore, when RF power levels change during the etch process, the wafer potential is driven to a changed value, typically nearly synchronous with the change in RF power. To avoid upsetting the voltage balance between both poles and the wafer, an automatic bias compensation, managed by the ESC power supply, has normally been utilized. In this compensation method the center point of the two pole voltages is driven to the same electrical potential as the wafer surface by equalizing both ESC pole currents. This, however, may lead to arcing on the wafer, since the ESC power supply is too slow to follow fast voltage changes on the wafer surface as they occur, for instance, during plasma ignition.
FIG. 1A shows a silicon wafer 12 that is damaged by an arcing event that may occur during an etching process. In this example, a surface potential (for example, −1000V) is generated at the top surface of the wafer which is being bombarded by electrons during an etching process. On the other hand, a substrate potential (e.g., 0V) exists in the substrate of the silicon wafer 12. Therefore, due to the potential difference between the top of the dielectric wafer surface and the wafer substrate, arcing 14 can occur between metal structures embedded in the dielectric of the wafer 12 since they establish differential voltage dividers of the surface-to-substrate potential drop. When the voltage differential between adjacent metal structures within the dielectric of the wafer exceeds the electrical breakdown strength of that dielectric, arcing will occur, leading to damage or destruction of the structures within the dielectric layer. In most cases, this will render the wafer unusable even though only as little as one die on the wafer may have been affected by the arcing. Consequently, if such occurrences are allowed to happen, wafer yields would be decreased and wafer production costs would increase.
FIG. 1B shows a graph 40 that shows a real-time surface potential during plasma ignition 42 in accordance with one embodiment of the present invention. The graph 40 shows a steady state surface potential 48, and an initial substrate potential 44 as it would be driven by the bias compensation circuit of the ESC power supply as it occurs during an etching process. The graph 40 shows the surface potential 42 as time progresses. The slope of the surface potential 42 at an early time is extremely steep so the surface potential 42 quickly increases to the steady state surface potential 48. Therefore, a very large voltage difference 46 may occur extremely quickly between the surface potential 42 and the initial substrate potential 44. Unfortunately, in this circumstance, the surface potential 42 increases too quickly for the compensation circuit of the ESC power supply. Therefore the substrate potential cannot be adjusted in a timely response to the surface potential increase. Therefore, wafer arcing as is described in reference to FIG. 1A may occur thereby damaging the wafer and decreasing wafer production yield and efficiency.
Therefore, there is a need for method that overcomes the problems of the prior art by using different bias voltages that correspond to different wafer etching stages and processes so in any suitable etching process, the bias voltage utilized can reduce wafer arcing.